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Design of FPGA-Board(Cyclone3)

by d-yu
on Di 19 Mai 2015

1.why the EEPROM are use Bank 5

Extemory Interface

Cyclone III Device Family

2. Different IO Banks can suppport different Voltage supply

The Cyclone III architecture supports the MultiVolt I/O interface feature that allows Cyclone III devices to interface with I/O systems that have different supply voltages.

3. The JTAG configuration

MSEL

the Voltag ...

Picking Resistors for LEDs

by d-yu
on Di 19 Mai 2015

Basics: Picking Resistors for LEDs

http://www.evilmadscientist.com/2012/resistors-for-leds/

ADC board design

by d-yu
on Do 14 Mai 2015

ADC板子设计

what is ADCLK-positive and negative ?
why AVDD and LVDD are equiquented with different capacities.?
FPGA 92,91 - ADCLK+/-
how to connect the lines of two adc chips to the FPGA board? what is the pin assignment?
普通模式的电压输出Vcm直接通过一个运放接给全差分运放作为ADC的输入数据。
Fibre 是什么玩意？磁珠
why in the original FPGA design the voltage of ...

ADC protection circuit design

by D.Yu
on Di 12 Mai 2015

Author: d-yu

ADC protection circuit design

5/12/2015 8:56:36 PM 方案全部错误，因为输入大电压时，运放无法正常工作！

There was a time when I thought zener diodes were great. Now I know that they're not. As a matter of fact they stink. This diode has a 4% tolerance at 250 µA ...

Questions of HW design

by d-yu
on Mo 11 Mai 2015

Questions

how to determine the resister for the Opamp?

usually will it set to 10k, and depends on the gain or the function. only limit the current
the input comem mode input be open or GND?
how to get 4 Voltage, problem! and 1V.?
what is the use of 10 ...

Generating Libs for Altium Design

by d-yu
on Fr 08 Mai 2015

Using the Ultra Librarian to generate the Libs.

Importing a library into Altium Designer

NOTE: make the files VISIBLE otherwise you will not see these files

UL_Form.dfm

UL_Form.pas

UL_Import.pas

UL_Import.PrjScr

so we can build our own Library and PCB footprint

Check Works

ctrl + M in Altium ...

Communication between FPGA and DSP28335

by d-yu
on Sa 25 April 2015

Communication between FPGA and DSP28335

This project want to creat a protocol between FPGA and DSP by using only 16 pins.

注意： VHDL的运行方式永远是并行的，所以进入某一个状态之后，它的输出ACK马上生效，而不像DSP中的C代码，进入一个状态后，需要一步一步执行，到最后才发送ACK信号。

引脚分配/Pin Assignment

Imgur

Logic in DSP - FSM

I mainly creat two functions: void Read_Adc(int addr0) and Send (). both of them ...

GPIO DIR change limit

by d-yu
on Mo 20 April 2015

GPIO 频率的问题

For the output behavior of GPIO its limit is 25Mhz

And for the input of GPIO, it can be synchronous to system clock.

Besides, I have done a little test to confirm the answer that I get. I put 10 normal instructions between the GPIO instructions. The 10 ...