Fake it until you make it

leben
Masterarbeit

Then end of Masterarbeit

by d-yu
on Mi 02 September 2015

Alles hat ein Ende!

The thing begined from a beginning , and end with an ending.

my works for the master thesis is almost done. the next step for me is to prepare the new life.

thesis

I endure the great pressure during the master thesis and finish all the jobs from ...

what is creepage and clearance

by d-yu
on Mi 02 September 2015

直接上图，不BB

creepage

GPIO control bugs for 6678L -2

by d-yu
on Do 13 August 2015

different setting !

        gpGPIO_regs->BANK_REGISTERS[0].SET_DATA = (1<<12);  // send address 10
        gpGPIO_regs->BANK_REGISTERS[0].CLR_DATA = (1<<11);
        gpGPIO_regs->BANK_REGISTERS[0].SET_DATA = (1<<14);  // send address 10

this is different with just

gpGPIO_regs->BANK_REGISTERS[0].OUT_DATA = 0x00005000

actually i just want to to set both 12th and 14th bit to 1 ...

GPIO control bugs for 6678L -1

by d-yu
on Mi 12 August 2015

NOTE for gpio control

gpGPIO_regs->BANK_REGISTERS[0].CLR_DATA =(1<<14); // DSP_ACK = 0 and gpGPIO_regs->BANK_REGISTERS[0].CLR_DATA |=(1<<14); // DSP_ACK = 0

are different!

But in the datasheet of TI, it says write a 0 to the CLR or SET register has no influence on the state pin.

However, as i ...

Linker to 6678L failed problem

by d-yu
on Fr 07 August 2015

Getting crazy with the connections problems

yestoday i came to the lab and aimed to finish the work!

but when i make everything ok and proceed the testing work of my communication protocol!

But But , the bloody 6678L board is noooooot working !!! i can not even download the program to ...

Rules and guidelines for drawing good schematics

by d-yu
on Di 28 Juli 2015

Rules and guidelines for drawing good schematics

Quota from Electronics stack Exchange

Orignal article!!!

A schematic is a visual representation of a circuit. As such, its purpose is to communicate a circuit to someone else. A schematic in a special computer program for that purpose is also a machine-readable description ...

Transplanting Protocol to DSP

by d-yu
on Mi 22 Juli 2015

test the protocol on 8 core dsp

Changing the pin Assignments and adjustment the Pin on both FPGA and DSP to the Communication Protocol.

results: it works!

problems:

wire house can not be installed propertly.
some stranges, by default state, all the pins are high voltage level
80 pin connecter ...

CCS6.1 breakpoint problem

by d-yu
on Di 21 Juli 2015

Debug problem of breakpoint

Problem:

can't not set breakpoint in the function
when click debug, No source available for main()
even i can place breakpoint, it will always pointed at the beginning of a function, can not be in the middle.

Solution:

Do not optimize the debug, and code ...

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