Tristate_FPGA

三态门-VHDL

1. 三态门的“Z”必须是大写，表示的意思是pin引脚三极管或者TTL的状态是截至状态的输出状态（简单理解为开路）。
2. 使用时，初始总线状态（db）必须是 ‘Z’

3. 以FPGA为对象:

   1. INOUT当 input 使用时: dataout <= db;
   2. INOUT当 output 使用时:

      if output_flag = 1 then
          db <= datain;
      else
          db <= 'Z';
      end if;
      

4. 简单来说，就是将双向口当输入时，随便用。当输出时，也随便用，但是用完之后要马上重新恢复到高阻态“Z”。

Right way to use it!

With inouts its better to split it up right at the top level into two signals data_from_outside and data_to_outside. Then your lower level needs three elements on the entity, one input vector, one output vector and a signal to say when to drive the outside data. Bidirectional signals don't sit well with records either.

The top level then needs to do:

data_pins <= data_to_outside when data_to_outside_enable = '1' else (others => 'Z');
data_from_outside <= data_pins;

From the point of view of style: put everything in one process. There's some debate about this, but many respected posters on comp.arch.fpga and >comp.lang.vhdl are of this opinion.