LVDS differential input pairs in FPGA

FPGA board design part

While routing the PCB board of FPGA I was wondering about why should i distribute the ADC input channels into different I/O BANKS. Then I decide to put all of them together but I also doubt if I can do it in this way?!

After a while, I found a BIG problem for our board design. WTF! Since we have 16 ADC differential input LVDS channels, but we only possess 14 available LVDS input channels in this FPGA.

Now the questions are:

1. If the I/O inputs can be identified to LVDS inputs?

2. If the differential Clock inputs channels can be borrowed?

Got some points from the Altera forum:

1. Altera devices have dedicated LVDS transmitters and receivers containing serialize or deserializer hard-IP blocks。You can also emulate LVDS, but those pins run slower and do not have a SERDES option. The handbook for the device you are using has details.
2. Cyclone V FPGAs operating the LVDS I/O standard need the associated bank to be powered at 2.5V. This is the way Altera have chosen to power LVDS transceivers but isn't how all manufacturers have chosen to drive LVDS interfaces.

sign...

明天找导师聊聊。。...

感觉要毕不了业了....

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